Runway bus
The Runway bus is a front-side bus developed by Hewlett-Packard for use by its PA-RISC microprocessor family. The Runway bus is a 64-bit wide, split transaction, time multiplexed address and data bus running at 120 MHz. This scheme was chosen by HP as they determined that a bus using separate address and data wires would have only delivered 20% more bandwidth for a 50% increase in pin count, which would have made microprocessors using the bus more expensive. The Runway bus was introduced with the release of the PA-7200 and was subsequently used by the PA-8000, PA-8200, PA-8500, PA-8600 and PA-8700 microprocessors. Early implementations of the bus used in the PA-7200, PA-8000 and PA-8200 had a theoretical bandwidth of 960 MB/s. Beginning with the PA-8500, the Runway bus was revised to transmit on both rising and falling edges of a 125 MHz clock signal, which increased its theoretical bandwidth to 2 GB/s. The Runway bus was succeeded with the introduction of the PA-8800, which used the Itanium 2 bus.
Bus features[1]
- 64-bit multiplexed address/data
- 20 bus protocol signals
- Supports cache coherency
- Three frequency options (1.0, 0.75 and 0.67 of CPU clock — 0.50 apparently was later added)
- Parity protection on address/data and control signal
- Each attached device contains its own arbitrator logic
- Split transactions, up to six transactions can be pending at once
- Snooping cache coherency protocol
- 1-4 processors "glueless" multi-processing (no support chips needed)
- 768 MB/s sustainable throughput, peak 960 MB/s at 120 MHz
- Runway+/Runway DDR: On PA-8500, PA-8600 and PA-8700, the bus operates in DDR (double data rate) mode,
- resulting in a peak bandwidth of about 2.0 GB/s (Runway+ or Runway DDR) with 125 MHz
Most machines use the Runway bus to connect the CPUs directly to the IOMMU (Astro, U2/Uturn or Java) and memory. However, the N class and L3000 servers use an interface chip called Dew to bridge the Runway bus to the Merced bus that connects to the IOMMU and memory.
References
- Bryg, William R.; Chan, Kenneth K.; Fiduccia, Nicholas S. (February 1996). "A High Performance, Low Cost Multiprocessor Bus for Workstations and Midrange Servers" (PDF). Hewlett-Packard Journal.
- Gwennap, Linley (November 17, 1997). "PA-8500's 1.5M Cache Aids Performance". Microprocessor Report.
- ^ "PA-RISC Buses on HP 9000 Computers – OpenPA.net".
- v
- t
- e
- System bus
- Front-side bus
- Back-side bus
- Daisy chain
- Control bus
- Address bus
- Bus contention
- Bus mastering
- Network on a chip
- Plug and play
- List of bus bandwidths
- SS-50 bus
- S-100 bus
- Multibus
- Unibus
- VAXBI
- MBus
- STD Bus
- SMBus
- Q-Bus
- Europe Card Bus
- ISA
- STEbus
- Zorro II
- Zorro III
- CAMAC
- FASTBUS
- LPC
- HP Precision Bus
- EISA
- VME
- VXI
- VXS
- VPX
- NuBus
- TURBOchannel
- MCA
- SBus
- VLB
- HP GSC bus
- InfiniBand
- Ethernet
- UPA
- PCI
- PCI Extended (PCI-X)
- PXI
- PCI Express (PCIe)
- AGP
- Compute Express Link (CXL)
- Direct Media Interface (DMI)
- RapidIO
- Intel QuickPath Interconnect
- NVLink
- HyperTransport
- Intel Ultra Path Interconnect
- Coherent Accelerator Processor Interface (CAPI)
- SpaceWire
- ST-506
- ESDI
- IPI
- SMD
- Parallel ATA (PATA)
- Bus and Tag
- DSSI
- HIPPI
- Serial ATA (SATA)
- SCSI
- ESCON
- Fibre Channel
- SSA
- SATAe
- PCI Express (via AHCI or NVMe logical device interface)
- Multidrop bus
- CoreConnect
- AMBA (AXI)
- Wishbone
- SLIMbus
![](http://upload.wikimedia.org/wikipedia/en/thumb/9/96/Symbol_category_class.svg/16px-Symbol_category_class.svg.png)